1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly NMOS-type integrated circuits having fine-line geometries with threshold adjust and arsenic source/drain implants.
2. Background of the Relevant Art
Fabrication of an NMOS device generally begins with a p-type silicon substrate having a plurality of source/drain n-type regions implanted into the substrate or well. A channel region is formed within the substrate and between corresponding pairs of source/drain regions. A gate oxide and control polysilicon are formed above the channel in order to controllably activate an inversion area within the channel and between source and drain conductors. In FIG. 1, a top view of an active device 10 is shown having control polysilicon 12 placed above channel region 14, wherein channel 14 is configured between source and drain implants 16 and 18, respectively.
Very large scale integration (VLSI) processing dictates that active devices 10 be placed close to one another in a dense fashion. As such, source and drain regions 16 and 18 are implanted at a shallow depth, and are separated from one another by a short channel 14. The distance between source and drain regions is often referred to as the "physical channel length". However, after implantation and subsequent diffusion of the source and drains, the distance between the source and drain regions becomes less than the physical channel length, and is often referred to as the "effective channel length" (Leff).
Referring to a cross-sectional view along plane A--A of FIG. 1, FIG. 2 illustrates Leff as the distance between the inner diffusion boundaries of source and drain regions 16 and 18. As NMOS devices become more dense, Leff becomes extremely small. A well-known phenomena, denoted as "short channel effects" (SCE) generally arises whenever Leff becomes less than approximately 3 .mu.m. SCE becomes a dominant part of MOS device behavior at small Leffs. Generally speaking, SCE impacts device operation by, inter alia, reducing device threshold voltages and increasing subthreshold currents. A problem related to SCE, however, altogether different, is the problem of "hot carrier effect" (HCE). HCE is a phenomena by which hot holes and electrons can overcome the potential energy barrier between the silicon and overlying silicon dioxide in order to cause hot carriers to inject into the gate oxide. HCE thereby relates to carrier impact at the substrate topography, whereas SCE relates to carrier impact within the substrate itself.
SCE is most pronounced by its affect upon threshold voltages. As Leff is reduced, measured value of threshold voltage of an NMOS enhancement-mode device becomes less positive, while threshold of an NMOS depletion-mode device becomes more negative. Hence, some of the channel region becomes partially depleted without any influence of a gate voltage. Since some of the channel is depleted absence gate bias, less gate charge is required to invert the channel in short-channel devices than in long-channel devices with comparable substrate doping. Another problem associated with SCE is the impact upon subthreshold currents. In short-channel devices, larger subthreshold current values are observed at lower voltages than in long-channel devices. Two of the primary causes of increased subthreshold current are: (i) punchthrough and (ii) drain-induced barrier lowering (DIBL). Punchthrough results from the widening of the drain depletion region when a reverse-biased voltage is placed on the drain. The electric field of the drain may eventually penetrate to the source area, thereby reducing the potential energy barrier of the source-to-body junction. Recent studies have indicated that in devices which use ion implantation to adjust threshold voltages, the barrier is lowest away from the silicon-silicon dioxide interface. As a result, punchthrough current flows below the surface region and deep within the substrate bulk material. Contrary to punchthrough current, DIBL-induced current occurs mostly at the substrate surface. Application of a drain voltage can cause the surface potential to be lowered, resulting in a lowered potential energy barrier at the surface and causing the subthreshold current in the channel near the silicon-silicon dioxide interface to be increased. This implies that subthreshold current at the surface due to DIBL is expected to become larger as the gate voltage approaches threshold.
As shown above, there are numerous effects resulting from SCE including, but not limited to, threshold, punchthrough and DIBL skews. Unlike SCE, HCE occurs above the substrate in the substrate topography and, more particularly, in the gate oxide. This is because the gate oxide normally contains empty electron states, also known as "traps", which can be filled by the injection of hot carriers. Due to the polarity of trapped charge, the resulting shift in the NMOS device threshold is positive. The result of HCE is therefore the same as SCE for threshold skew, but the means for achieving the deleterious result is altogether different. Further, HCE does not demonstrate bulk or surface-induced current such as punchthrough- and DIBL-induced current.
Due to their dissimilarities, different solutions are needed to overcome the problems of HCE and SCE. A popular processing methodology used to minimize HCE is to apply double-diffused drains or lightly-diffused drains (LDDs) in the active area between the source/drain regions and the channel area. The purpose of LDDs is to absorb a majority of the electron potential into the drain and thus reduce the maximum electric field therein. Illustrated in FIG. 2 are LDDs 20 implanted into the active area prior to placement of sidewall spacers 22 at the sides of polysilicon 12. The purpose and formation of sidewall spacers 22 are well known in the art. Generally speaking, spacers 22 allow subsequent implant of source and drain regions 16 and 18 spaced from the channel at a higher dose than LDDs 20. The lighter dose LDDs absorbs virtually the entire voltage drop between the drain (or source) and the channel. The electric field is thereby reduced, resulting in a lessening of the hot carriers being injected into the gate oxide 24. As described in Ng, et al., "Suppression of Hot-Carrier Degradation in Si MOSFET's by Germanium Doping", Electron Device Letters, Vol 11, No. 1, January, 1990, germanium co-implanted with the LDD areas further enhances the LDD structure. Germanium, being electrically neutral, is purposefully placed between the channel and the source/drain areas in order to minimize injection of "lucky" hot carriers in the gate oxide.
SCE, on the other hand, presents punchthrough (bulk) current path 26 and DIBL (surface) current path 28 from drain 18 to source 16, as shown in FIG. 2. In order to minimize punchthrough path 26, substantial research has focused upon using germanium co-implanted with source/drain phosphorous. See, e.g., Pfiester, et al., "Improved MOSFET Short Channel Device Using Germanium Implantation", IEEE Electron Device Letters, Vol 9, No 7, July, 1988. Germanium is therefore known as having an inhibiting effect upon phosphorous junction depths, thereby providing reduced punchthrough current in the bulk and thereby improving SCE. More recent studies with fluorine indicates the retardant effect of fluorine upon both the junction depth as well as the lateral diffusion of phosphorous. See, e.g., Lin, et al., "The Effect of Fluorine on MOSFET Channel Length", IEEE Electron Device Letters, Vol. 14, No. 10, October, 1993. Co-implant of fluorine with LDD regions limits the lateral diffusion of phosphorous source/drain regions and thereby affords a longer Leff.
Dissimilar from the problems of punchthrough current, DIBL-induced current 28 arises primarily from the operation of, or voltage placed upon, the drain region. A popular technique used to minimize DIBL current generally involves placing a threshold-adjust implant at the substrate surface in order to minimize current therethrough. Boron is often lightly implanted at the surface, as shown by reference numeral 30, in order not only to increase threshold voltages in channel 14, but also to offset the lowering of the surface potential naturally resulting from drain bias. As the gate voltage approaches threshold, subthreshold current at the surface due to DIBL will be lowered as a result of boron diffusion 30. Unfortunately, boron, being of opposite impurity type than either the LDD 20 or source/drain 16/18, allows migration of the electrically active boron dopant from the channel region to the adjacent LDDs or source/drain. The phenomena is often referred to as "boron redistribution and segregation". Many studies have evidenced this phenomena and have attributed its result to threshold rolloff and DIBL-induced current. See, e.g., Acovic, et al., "Arsenic Source and Drain Implant-Induced Degradation of Short-Channel Effects in NMOSFET's", IEEE Electron Device Letters, Vol. 14, No. 7, July, 1993.
As a result of recent studies, the advantages of boron implant 30 are offset by the demonstration of boron migration from the edges of channel 14 into the adjacent LDDs or source/drains during subsequent furnace or rapid thermal annealing. While arsenic provides higher conductivity at the source and drain, it also disrupts or damages the substrate lattice to a greater extent than older phosphorous source/drain implants. In order to remove the damage caused by arsenic implant, high temperature annealing at approximately 900.degree. to 1000.degree. C. is necessary. In the course of annealing, boron atoms 32, shown in FIG. 3 (i.e., FIG. 3 being a detailed view along area C of FIG. 2), migrate or diffuse (i.e., segregate) from the edges of channel 14 to LDD 20 and source/drain areas 16/18. The boron atoms can diffuse across substitutional (or vacant) sites or through interstitial movement. Due to a larger number of vacancies in regions 20, 18 and 16 caused by phosphorous atoms 33 (LDD implant) and arsenic atoms 34 (source/drain implant) intra-lattice disruption, vacancy and/or interstitialcy motion is greatly enhanced. Movement of boron atoms from the edge of channel 14 to adjacent implant areas along the substrate surface increases dramatically DIBL-induced currents and allows threshold rolloff. In order to counteract those problems, conventional solutions have pointed to applying additional boron "halo" implants around the source and drain to offset the boron redistribution void caused by anneal movement. See, e.g., Acovic, et al., "Arsenic Source and Drain Induced Degradation of Short-Channel Effects in NMOSFET's", IEEE Electron Device Letters, Vol. 14, No. 7, July, 1993; and Acovic, et al., "Enhanced Short-Channel Effects of NMOSFET's Due to Boron Redistribution Induced By Arsenic Source and Drain Implant", IEDM, 1992.
Placement of an electrically active dopant such as boron to offset the boron channel redistribution problem only adds to the threshold skewing problems of SCE. The purpose of threshold adjust implant is to specifically control and define consistent thresholds for each and every device across the semiconductor wafer. Indiscriminately implanting a boron halo at the channel edge may cause further increase of threshold beyond a desired amount in only a select few of devices but not all devices. Accordingly, tight control of threshold and consistent reduction of DIBL-induced current cannot necessarily be achieved by adding to or taking away from the threshold adjust boron, as it currently exists within the channel area. Still further, a boron implant into or around the source and drain regions adversely effects the source/drain junction capacitance thereby decreasing the operating ("on/off") speed of the device. While it is important to maintain arsenic as the preferred source/drain implant material, it is also important to control the problems of boron redistribution without adding additional electrically active dopants to the channel or within the arsenic areas.
It is also important to tightly control another phenomena known as narrow gate-width effect (NGWE) related to SCE but altogether different. NGWE refers to the encroachment of channel stop dopants such as boron under the field oxide edges at the sides of the gate. Referring to FIG. 4, a cross sectional view of the gate width along plane B--B of FIG. 1 is shown. Channel stop dopant 36 is shown placed across the upper surface of the substrate not only to adjust threshold voltages in the channel (as shown by reference numeral 30 of FIG. 2) but also to physically and electrically block lateral out-diffusion of source/drain implants underneath field oxide 38. As channel lengths become small, so do channel widths. A result being a greater likelihood of drain/source and/or channel voltages causing field-induced encroachment of dopants 36 into the adjacent channel or source/drain regions. Encroachment, shown by arrow 40 provides an even smaller channel width, i.e., a channel width, Wmod, which is less than the physical channel width, W.